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1 features ? low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 5.5v) ? user-selectable internal organization ? 1k: 128 x 8 or 64 x 16 ? three-wire serial interface ? 2 mhz clock rate (5v) ? self-timed write cycle (10 ms max) ? high reliability ? endurance: 1 million write cycles ? data retention: 100 years ? automotive grade devices available ? 8-lead jedec pdip, 8-lead jedec soic, 8-lead eiaj soic, 8-lead ultra thin mini-map (mlp 2x3), 8-lead tssop and 8-ball dbga2 packages description the at93c46 provides 1024 bits of serial electrically erasable programmable read- only memory (eeprom), organized as 64 wo rds of 16 bits each (when the org pin is connected to vcc), and 128 words of 8 bi ts each (when the org pin is tied to ground). the device is optimized for use in many industrial and commercial applica- tions where low-power and low-voltage operations are essential. the at93c46 is available in space-saving 8-lead pdip, 8-lead jedec soic, 8-lead eiaj soic, 8-lead ultra thin mini-map (mlp 2x3), 8-lead tssop, and 8-lead dbga2 packages. the at93c46 is enabled through the chip select pin (cs) and accessed via a three-wire serial interface consisting of data input (di), data output (do), and shift clock (sk). upon receiving a read instru ction at di, the address is decoded and the data is clocked out serially on the do pi n. the write cycle is completely self-timed, and no separate erase cycle is required bef ore write. the write cycle is only enabled when the part is in the erase/write enable state. when cs is brought high following the initiation of a write cycle, the do pi n outputs the ready/busy status of the part. the at93c46 is available in 2.7v to 5.5v and 1.8v to 5.5v versions. table 1. pin configurations pin name function cs chip select sk serial data clock di serial data input do serial data output gnd ground vcc power supply org internal organization dc don?t connect three-wire serial eeprom 1k (128 x 8 or 64 x 16) at93c46 note: not recommended for new design; please refer to at93c46d datasheet. 5140b?seepr?2/07 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd vcc dc org gnd c s s k d1 d0 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 1 2 3 4 8 7 6 5 dc vcc cs sk org gnd do di 1 2 3 4 8 7 6 5 vcc dc org gnd cs sk di do 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead soic 8-lead dbga2 8-lead pdip 8-lead soic rotated (r) (1k jedec only) 8-lead ultra thin mini-map (mlp 2x3) 8-lead tssop bottom view bottom view
2 at93c46 5140b?seepr?2/07 figure 1. block diagram note: when the org pin is connected to vcc, th e ?x 16? organization is selected. when it is connected to ground, the ?x 8? organization is selected. if the org pin is left uncon- nected and the application does not load the in put beyond the capability of the internal 1 meg ohm pullup, then the ?x 16? organization is selected. the feature is not available on the 1.8v devices. for the at93c46, if ?x 16? organization is the mode of choice and pin 6 (org) is left unconnected, atmel recommends using the at93c46a device. for more details, see the at93c46a datasheet. absolute maximum ratings* operating temperature ......................................? 55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at93c46 5140b?seepr?2/07 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (do) 5 pf v out = 0v c in input capacitance (cs, sk, di) 5 pf v in = 0v table 3. dc characteristics applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v, t ae = -40 c to +125 c, v cc = +1.8v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max unit v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc supply current v cc = 5.0v read at 1.0 mhz 0.5 2.0 ma write at 1.0 mhz 0.5 2.0 ma i sb1 standby current v cc = 1.8v cs = 0v 0 0.1 a i sb2 standby current v cc = 2.7v cs = 0v 6.0 10.0 a i sb3 standby current v cc = 5.0v cs = 0v 17 30 a i il input leakage v in = 0v to v cc 0.1 1.0 a i ol output leakage v in = 0v to v cc 0.1 1.0 a v il1 (1) input low voltage 2.7v v cc 5.5v ? 0.6 0.8 v v ih1 (1) input high voltage 2.0 v cc + 1 v il2 (1) input low voltage 1.8v v cc 2.7v ? 0.6 v cc x 0.3 v v ih2 (1) input high voltage v cc x 0.7 v cc + 1 v ol1 output low voltage 2.7v v cc 5.5v i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = ? 0.4 ma 2.4 v v ol2 output low voltage 1.8v v cc 2.7v i ol = 0.15 ma 0.2 v v oh2 output high voltage i oh = ? 100 av cc ? 0.2 v
4 at93c46 5140b?seepr?2/07 note: 1. this parameter is characterized and is not 100% tested. table 4. ac characteristics applicable over recommended operating range from t ai = ? 40c to + 85c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter test condition min typ max units f sk sk clock frequency 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 0 0 0 2 1 0.25 mhz t skh sk high time 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t skl sk low time 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t cs minimum cs low time 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t css cs setup time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 50 50 200 ns t dis di setup time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 100 100 400 ns t csh cs hold time relative to sk 0 ns t dih di hold time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 100 100 400 ns t pd1 output delay to ?1? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t pd0 output delay to ?0? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t sv cs to status valid ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 250 250 1000 ns t df cs to do in high impedance ac test cs = v il 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 100 100 400 ns t wp write cycle time 10 ms 4.5v v cc 5.5v 0.1 3 ms endurance (1) 5.0v, 25c 1m write cycles
5 at93c46 5140b?seepr?2/07 note: the xs in the address field represent don?t care values and must be clocked. functional description the at93c46 is accessed via a simple and versatile three-wire serial communication interface. device operation is controlled by seven instructions issued by the host pro- cessor. a valid instruction starts with a rising edge of cs and consists of a start bit (logic ?1?) followed by the appropriate op code and the desired memory address location. read (read): the read (read) instruction contains the address code for the mem- ory location to be read. after the instruction and address are decoded, data from the selected memory location is available at th e serial output pin do. output data changes are synchronized with the rising edges of serial clock sk. it should be noted that a dummy bit (logic ?0?) precedes the 8- or 16-bit data output string. erase/write enable (ewen): to assure data integrity, the part automatically goes into the erase/write disable (ewds) state when power is first applied. an erase/write enable (ewen) instruction must be executed first before any programming instructions can be carried out. please note that once in the ewen state, programming remains enabled until an ewds instruction is executed or v cc power is removed from the part. erase (erase): the erase (erase) instruction pr ograms all bits in the specified memory location to the logical ?1? state. the self-timed erase cycle starts once the erase instruction and address are decoded. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ?1? at pin do indicates that the selected memory location has been erased and the part is ready for another instruction. write (write): the write (write) instruction contains the 8 or 16 bits of data to be written into the specified memory loca tion. the self-timed programming cycle t wp starts after the last bit of data is received at se rial data input pin di. the do pin outputs the read/busy status of the part if cs is bro ught high after being kept low for a minimum of 250 ns (t cs ). a logic ?0? at do indicates that prog ramming is still in progress. a logic ?1? indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and th e part is ready for further instructions. a ready/busy status cannot be obtained if the cs is brought high after the end of the self- timed programming cycle twp. table 5. instruction set for the at93c46 instruction sb op code address data comments x 8 x 16 x 8 x 16 read 1 10 a 6 ? a 0 a 5 ? a 0 reads data stored in memory, at specified address ewen 1 00 11xxxxx 11xxxx write enable must precede all programming modes erase 1 11 a 6 ? a 0 a 5 ? a 0 erases memory location a n ? a 0 write 1 01 a 6 ? a 0 a 5 ? a 0 d 7 ? d 0 d 15 ? d 0 writes memory location a n ? a 0 eral 1 00 10xxxxx 10xxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v wral 1 00 01xxxxx 01xxxx d 7 ? d 0 d 15 ? d 0 writes all memory locations. valid only at v cc = 4.5v to 5.5v ewds 1 00 00xxxxx 00xxxx disables al l programming instructions
6 at93c46 5140b?seepr?2/07 erase all (eral): the erase all (eral) instructio n programs every bit in the mem- ory array to the logic ?1? state and is prim arily used for testing purposes. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the eral instruction is valid only at v cc = 5.0v 10%. write all (wral) : the write all (wral) instruction programs all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the wral instruction is valid only at v cc = 5.0v 10%. erase/write disable (ewds): to protect against accidental data disturb, the erase/write disable (ewds) instruction di sables all programming modes and should be executed after all programming operations. the operation of the read instruction is independent of both the ewen and ewds inst ructions and can be executed at any time. timing diagrams figure 2. synchronous data timing note: 1. this is the minimum sk period. s table 6. organization key for timing diagrams i/o at93c46 (1k) x 8 x 16 a n a 6 a 5 d n d 7 d 15
7 at93c46 5140b?seepr?2/07 figure 3. read timing figure 4. ewen timing figure 5. ewds timing high impedance t cs c s 11 ... 00 1 s k di t cs c s t cs s k di 1 0 000 ...
8 at93c46 5140b?seepr?2/07 figure 6. write timing figure 7. wral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. figure 8. erase timing s k c s t cs t wp 11 a n d n 0a0d0 ... ... di d o high impedance busy ready c s s k di d o high impedance busy ready 1 0 0 1 ... d n t cs t wp ... d0 0 sk 1 1 ... 1 c s di a n t cs t sv t df t wp a n-1 a n-2 a0 check status standby ready busy d o high impedance high impedanc e
9 at93c46 5140b?seepr?2/07 figure 9. eral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. sk c s di 1 1 00 0 d o high impedance high impedanc e ready busy check status standby t wp t cs t sv t df
10 at93c46 5140b?seepr?2/07 notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the table 3 on page 3 and table 4 on page 4. not recommended for new design. please refer to at93c46d datasheet. 2. ?u? designates green package and rohs compliant. 3. ?h? designates green package and rohs compliant, with nipdau lead finish 4. available in waffle pack and wafer form, order as sl788 for inkless wafer form. bumped die available upon request. at93c46 ordering information (1) ordering code package operation range at93c46-10pu-2.7 (2) at93c46-10pu-1.8 (2) at93c46-10su-2.7 (2) at93c46-10su-1.8 (2) at93c46w-10su-2.7 (2) at93c46w-10su-1.8 (2) at93c46-10tu-2.7 (2) at93c46-10tu-1.8 (2) at93c46y1-10yu-1.8 (2) (not recommended for new designs) at93c46y6-10yh-1.8 (3) at93c46u3-10uu-1.8 (2) 8p3 8p3 8s1 8s1 8s2 8s2 8a2 8a2 8y1 8y6 8u3-1 lead-free/halogen-free/ industrial temperature ( ? 40 c to 85 c) at93c46-w1.8-11 (4) die sale industrial ( ? 40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline (eiaj soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8u3-1 8-ball, die ball grid array package (dbga2) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footprin t, non-leaded, miniature array package (map) 8y6 8-lead, 2.00 mm x 3.00 mm body, 0.50mm pitch, ultra-t hin mini-mao, dual no lead package. (dfn), (mlp 2x3mm) options ? 2.7 low voltage (2.7v to 5.5v) ? 1.8 low voltage (1.8v to 5.5v) r rotated pinout
11 at93c46 5140b?seepr?2/07 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
12 at93c46 5140b?seepr?2/07 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
13 at93c46 5140b?seepr?2/07 8s2 ? eiaj soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 10/7/03 8s2 c common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b and c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 ? 0? 8? e 1.27 bsc 4 end view side view e b a a1 d e n 1 c e1 ? l top view
14 at93c46 5140b?seepr?2/07 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
15 at93c46 5140b?seepr?2/07 8u3-1 ? dbga2 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. po 8 u 3 -1 a 6/24/0 3 common dimensions (unit of me asu re = mm) symbol min nom max note 8u3-1, 8 - ba ll, 1.50 x 2.00 mm body, 0.50 mm pitch, s m a ll die b a ll grid arr a y p a ck a ge (dbga2) a 0.71 0. 8 1 0.91 a1 0.10 0.15 0.20 a2 0.40 0.45 0.50 b 0.20 0.25 0. 3 0 d 1.50 b s c e 2.00 b s c e 0.50 b s c e1 0.25 ref d 1.00 b s c d1 0.25 ref 1. dimen s ion ? b? i s me asu red a t the m a xim u m s older ba ll di a meter. thi s dr a wing i s for gener a l inform a tion only. bottom view 8 s older ball s b d e top view pin 1 ball pad corner a s ide view a 2 a 1 4 5 pin 1 ball pad corner 3 1 e 2 6 7 8 d (e1) (d1) 1.
16 at93c46 5140b?seepr?2/07 8y6 ? mini-map 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8y6 , 8-lead 2.0 x 3.0 mm body, 0.50 mm pitch, utlra thin mini-map, dual no lead package (dfn) ,(mlp 2x3) c 8y6 8/26/05 notes: 1. this drawing is for general information only. refer to jedec drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. common dimensions (unit of measure = mm) symbol min nom max note d 2.00 bsc e 3.00 bsc d2 1.40 1.50 1.60 e2 - - 1.40 a - - 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 a3 0.20 ref l 0.20 0.30 0.40 e 0.50 bsc b 0.20 0.25 0.30 2 a2 b (8x) pin 1 id pin 1 index area a1 a3 d e a l (8x) e (6x) 1.50 ref. d2 e2
17 at93c46 5140b?seepr?2/07 revision history doc. rev. date comments 5140b 2/2007 implemented revision history. added note to page 1 and ordering information; ?not recommended for new design; please refer to at93c46d datasheet?.
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